1. Field of the Invention
The present invention relates to an integrated circuit, and more specifically relates to an integrated circuit including a plurality of depletion type MOS transistors with varying threshold voltages and a method of manufacturing the same.
2. Description of Related Art
FIG. 7 is a circuit diagram showing a portion of a solid-state imaging device in general use. Photosensitive cells 101, each composed of a photodiode 103, a transfer gate 104, a reset transistor 105 and an amplify transistor 106, are arranged in a matrix form. Each of the photosensitive cells 101 is connected at a contact 109 to a constant-current power supply 108 and to a noise suppressing circuit 102 composed of transistors 111 and 113 and capacitors 112 and 114. The noise suppressing circuit 102 is connected to a horizontal signal line 124 via a horizontal transistor 121 controlled by a horizontal driver circuit 122.
The above-described circuit is a typical circuit of a pixel, and in the circuit, for applications including potential resetting and potential transmission such as performed by the reset transistor 105, the horizontal transistor 121, and the transistors 113 and 123 with respect to a power supply voltage, MOS transistors with varying threshold voltages are used. As such a MOS transistor, generally, a depletion type transistor having a negative threshold voltage is used.
Conventionally, such a depletion type transistor is formed by a method in which an enhancement type transistor with a channel region doped with an impurity is used, and an impurity having conductivity reversed from that of the impurity is introduced into the channel region.
Furthermore, there is a method for controlling threshold voltages of a plurality of transistors by introducing an impurity of a conductivity type (first conductivity type) reversed from that of a second conductivity type substrate into a channel (see, for example, JP 2000-323587 A). In a CMOS semiconductor device composed of a plurality of MOS transistors with varying threshold voltages, first, a second conductivity type well region and a first conductivity type well region are formed on a substrate. Next, a process step of implanting ions into a surface region of the first conductivity type well region is performed so that a first conductivity type impurity layer for threshold voltage control is formed. Then, on a surface region of at least one of the well region in which the first conductivity type impurity layer is formed and the well region in which the first conductivity type impurity layer is not formed, a second conductivity type impurity layer for threshold voltage control is formed by the ion implantation process step. By this manufacturing method, a transistor can be formed with ion implantation performed a number of times fewer than the number of values of the varying threshold voltages.
Furthermore, there is a method for controlling a threshold voltage of a depletion type transistor using arsenic (see, for example, JP 60-134468 A). This method allows a threshold voltage to be controlled by varying an amount of arsenic to be implanted, and thus an extremely high-precision transistor can be obtained that is hardly affected by, for example, processing precision in lithography, dry etching or the like, the intrusion of a field oxide film resulting from a LOCOS method or the like, and the intrusion of a channel stopper.
FIGS. 8A to 8G are cross-sectional views showing as an example process steps of manufacturing a conventional semiconductor device including a depletion type NMOS transistor. A N-channel enhancement type transistor represented by the amplify transistor 106 shown in FIG. 7 is formed in a region A, and a depletion type transistor represented by the reset transistor 105 shown in FIG. 7 is formed in a region B.
First, as shown in FIG. 8A, an element isolation region 144 is formed selectively in a silicon substrate 131. Next, as shown in FIG. 8B, using a resist 151 as a mask, a p-type impurity is implanted so that a p-well region 132 is formed on the silicon substrate 131. Then, similarly, using the same mask (resist 151), a p-type impurity is implanted so that a channel stop layer 133 is formed. Subsequently, using the same mask (resist 151), a p-type impurity is implanted further so that p-type impurity layers 161 and 162 are formed, and the resist 151 is removed.
Next, as shown in FIG. 8C, a resist 154 that covers the region A and has an opening in the region B is pattern-formed. Then, using the resist 154 as a mask, a n-type impurity having conductivity reversed from that of the p-type impurity is implanted into the p-type impurity layer 162 in the region B so that a n-type impurity layer 163 is formed and a threshold voltage of the depletion type transistor is determined. Next, as shown in FIG. 8D, the resist 154 is removed, and an oxide film 156 and polysilicon 157 are formed. Subsequently, a resist 158 is pattern-formed.
Next, using the resist 158 as a mask, the polysilicon 157 and the oxide film 156 are dry-etched and the resist 158 is removed so that, as shown in FIG. 8E, a gate electrode 142 and a gate oxide film 141 are defined. Then, a n-type impurity is implanted so that LDD (Lightly Doped Drain) regions 136 and 137 are formed, thereby defining implantation regions 134 and 135. Subsequently, as shown in FIG. 8F, a gate side-wall insulation film (side-wall insulation film) 143 is formed on side faces of the gate electrode 142.
Next, as shown in FIG. 8G, using the gate electrode 142 and the gate side-wall insulation film 143 as a mask, a n-type impurity is implanted so that source/drain regions 139 and 140 are formed in the LDD regions 136 and 137, respectively.
In the above-described manner, a plurality of MOS transistors with varying threshold voltages can be formed on a common substrate.
Furthermore, in order to obtain an improved characteristic of a solid-state imaging device, it is necessary that a coefficient of fluctuation of a surface potential in a channel region of a depletion type transistor with respect to a gate voltage be increased so that a dynamic range of a floating diffusion 107 is increased. It is desirable that the dynamic range be as large as possible. The dynamic range of the floating diffusion 107 refers to a ratio between a signal obtained when the reset transistor 105 is OFF and a signal obtained when the reset transistor 105 is ON.
Herein, a coefficient of potential fluctuation of a surface potential in a channel region of a depletion type transistor with respect to a gate voltage is defined as a “modulation degree”. The modulation degree is one of the indices of the capabilities of a depletion type transistor. FIG. 9 is a band diagram showing depletion of a MOS transistor. A gate voltage VG is divided according to a gate oxide film thickness capacity Cox and a depletion layer capacity Cdep, and therefore, a surface potential Φs with respect to a gate voltage is expressed by:Φs=[Cox/(Cox+Cdep)]×VG. The modulation degree refers to a fluctuation amount ΔΦs of the surface potential Φs with respect to a fluctuation amount ΔVG of the gate voltage VG and thus is expressed by:Modulation degree=ΔΦs/ΔVG=Cox/(Cox+Cdep)  (Equation 1).Accordingly, in the case where a surface potential is allowed to fluctuate in accordance with a gate voltage, the modulation degree has a value of 1.
Each of FIGS. 10A and 10B is a diagram showing internal potentials of a source, a gate and a drain in a depletion type transistor in a conducting mode (ON) and in a power cut-off mode (OFF), respectively, in the case where the depletion type transistor is used as, for example, the reset transistor 105 shown in FIG. 7. FIG. 10A shows a case where the modulation degree is high, and FIG. 10B shows a case where the modulation degree is low.
As shown in FIGS. 10A and 10B, each of ΔΦs 1 and ΔΦs 2 indicates a fluctuation amount of a surface potential immediately under a gate with respect to a gate voltage. As shown in FIGS. 10A and 10B, a difference between ΔΦs 1 and ΔΦs 2 produced when the gates are supplied with the same voltage (VG=Von) is derived from a difference in modulation degree. When the modulation degree is high, the surface potential has a large fluctuation amount, thereby allowing a surface potential immediately under the gate in the conducting mode to be not higher than a reset potential. In this case, as shown in FIG. 10A, a signal charge 151 that has been stored temporarily in a source region in the power cut-off mode is discharged almost entirely into a drain region, with only a slight amount left in the source region.
On the other hand, when the modulation degree is low, the surface potential has a small value of the fluctuation amount ΔΦs. As shown in FIG. 10B, this causes a surface potential immediately under the gate to be higher than a reset potential, so that a portion of the signal charge 151 failing to exceed the surface potential immediately under the gate results as a residual charge 152.
As the miniaturization of a transistor is advanced with the use of a lower voltage in an integrated circuit and a size reduction of an integrated circuit, there arises a problem that in an enhancement type transistor, punch through occurs in a channel region (especially, in an implantation region) due to a short channel effect to cause a considerable amount of leakage current. With respect to this problem, conventionally, the occurrence of leakage current is suppressed by the formation of a pocket diffusion layer in contact with a source or a drain. Meanwhile, as has been described already with reference to FIG. 7, the transistors such as indicated by 105, 121 and 123 are formed of a depletion type MOS transistor. In the circuit, these transistors function as commonly used switching transistors and thus can be in an off state. Hence, a depletion type MOS also should be formed so as not to cause punch through leakage current due to the short channel effect.
However, the above-described conventional depletion type transistor is formed by the easy method in which a LDD region and a source/drain region are formed simply by the implantation of an impurity having conductivity reversed from the conductivity of a semiconductor substrate and thus is not configured to prevent the occurrence of punchthrough leakage current. Therefore, if a source-drain distance of an implantation region is reduced as a result of the miniaturization of this configuration, punchthrough leakage current is likely to occur.
Furthermore, the above-described conventional depletion type transistor has difficulty in controlling a modulation degree and variations in the modulation degree and also presents a problem that the miniaturization of gate dimensions leads to an increase in variations in threshold voltage.
Variations in threshold voltage are attributable to the formation method in which a first conductivity type impurity and a second conductivity type impurity are introduced simultaneously into an implantation region. Even when the first conductivity type impurity and the second conductivity type impurity are implanted in a ratio of 1:1, these impurities do not necessarily cancel out the influences of each other. This brings about a state in which in one implantation region, an inactive portion of the first conductivity type impurity whose influence has been cancelled out, an inactive portion of the second conductivity type impurity that has cancelled out the influence, a portion of the first conductivity type impurity whose influence has failed to be cancelled out, and an active portion of the second conductivity type impurity that controls a threshold voltage coexist in a mixed state. The portions of the first conductivity type impurity and the second conductivity type impurity that are in an active state vary considerably due to a heat treatment performed during a processing process step and variations in dimensions. The miniaturization of gate dimensions has led to an increasing degree of such variations of these portions.
Furthermore, Equation 1 indicates that a modulation degree depends on a width of a depletion layer in the vicinity of a surface. With the depletion layer having an increased width, the depletion layer capacity Cdep decreases, and the modulation degree increases. That is, the modulation degree increases with increasing width of the depletion layer. However, in the conventional method of forming an implantation region, a second conductivity type impurity is implanted into an implantation region into which a first conductivity type impurity has been implanted, and thus a high-density pn junction is formed in the vicinity of a semiconductor surface, resulting in a decrease in the width of a depletion layer. This makes it difficult to increase the modulation degree. Moreover, for the same reason as described above in regard to variations in threshold voltage, it also is difficult to control variations in modulation degree.
While describing a method by which the problem of a manufacturing cost can be solved, JP 2000-323587 A makes no mention of these variations and thus hardly can solve the above-described problems. Furthermore, the structure described in JP 60-134468 A hardly can solve the above-described problems that have become more serious as miniaturization advances.